1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, more particularly, to a method and apparatus for self-calibrating timing circuits thereof.
2. Description of the Related Technology
Semiconductor integrated circuits are fabricated on, for example, a silicon wafer and may have a wide variance in speed of operation. Performance, even among the same type of integrated circuit, may vary widely in operational speed performance after layout by a factor of as much as 375 percent from slowest to fastest operating speed. This wide range of operating speeds results from process lot variations during fabrication of the integrated circuit wafer and resulting dice, variations in temperature and operating voltage of the integrated circuit dice during operation in a system.
Such wide variance in operating speed range typically causes design problems in timing between different devices such as set up and hold requirements and maximum clock speed. System circuit designs must take into account worst-case operating voltage and temperature characteristics of the integrated circuits utilized. Manufacturers must guarantee operating parameters that may be much less than actual products are capable of performing because worst-case conditions must be met. This results in a loss of circuit performance because operating parameters for worst-case conditions must always be maintained.
What is needed is a method and apparatus which automatically and continuously senses the relative performance of the integrated circuit during operation, and allows the operating speed of the circuit to be adjusted for best performance. It is, therefore, an object of the present invention to "self-calibrate" optimal performance parameters during operation over a wide range of temperatures and voltages encountered, and to compensate for operating parameter differences between integrated circuits resulting from variations during the fabrication process or in system operation.